1. Field of Invention
The present invention relates to CMOS microelectromechanical system (MEMS) device and the fabrication method. More particularly, the present invention relates to CMOS microelectromechanical system (MEMS) device with reduced damaged during etching process.
2. Description of Related Art
The CMOS MEMS device usually includes the CMOS circuit and the MEMS device, which are fabricated at the same substrate by semiconductor fabrication process. For the MEMS device with a sensing diaphragm, such as the microphone diaphragm or other application, a long etching process may be included for etching most of material including dielectric and silicon substrate. Since the device is under a long time of etching process, the MEMS structure may be damaged.
FIG. 1 is a cross-sectional view, schematically illustrating a conventional MEMS device at the stage to etch the substrate. As the issues noted by the present invention, in FIG. 1, after the structural dielectric layer 62 has been formed on the substrate 60, the substrate 60 needs to be etched to form a cavity and venting holes 64. However, since the depth of venting holes 64 are usually large and need a long etching time, an undercut usually occurs at the interface between the silicon oxide and the silicon substrate 60. The region 66 is expanded as shown at lower drawing. The undercut 69 occurs at the edge of the venting hole 64 between substrate 60 and the oxide 68. This causes defects of the MEMS device.
Further, it usually takes a long time to etch the dielectric so as to expose the diaphragm, another issue has also been noted by the invention. FIG. 2 is a cross-sectional view, schematically illustrating the process to etch the dielectric of the MEMS device for exposing the diaphragm. In FIG. 2, the structural dielectric layer 72 has bee formed on the substrate 70. The substrate 70 has been etched from the backside to have cavity and venting holes 74 as described in FIG. 1, in which the undercut still exits but not involved into the later issue in FIG. 2 for etching the dielectric of the structural dielectric layer 72. In order to expose the diaphragm, the isotropic etching process is performed form the back side and the front side. The dielectric at front side is etched to expose the diaphragm. However, the dielectric material under the diaphragm is not etched fast because the etchant can only pass the venting holes 74 to etch the dielectric material and it usually takes a long etching time. The issue then occurs.
When the substrate 70 is immersed in the etchant solution, the etching time for dielectric layer on back side is much longer than that on front side. Especially, the etching rate decreases significantly for the dielectric layer in the narrow gap between diaphragm and silicon substrate. Moreover, the etching rate also slows down when the etchant has to pass through vent holes 74 and cavity. Therefore, when the dielectric layer in the gap is removed, the exposed portions 76 of the diaphragm may be damaged due to the long exposure on etchant solution. As can be seen, it needs longer time to remove the oxide dielectric between the diaphragm and the substrate 70. It causes the diaphragm on the exposed 76, where the metal layer is exposed first, to be attacked easily by the etchant. In addition, most metal layers, e.g. TiN, exposed to etchant is formed by the structure of pillar grain with the grain boundary perpendicular to the surface of a diaphragm. The etchant is easy to penetrate the metal layer along the grain boundary into the dielectric of a diaphragm and damage the diaphragm. This conventional issue considered by the present invention and the solution proposed by the present invention will be discussed later in FIGS. 21 and 22.
The invention has noted at least the foregoing issues. How to at least reduce the issues need to be developed.